Synopsys Tutorial

VCS - Verilog Logic Simulation Tool

Authors: Jinsik Yun, Dr. Dong S. Ha

This tutorial shows a Verilog simulation process using VCS. You have to follow these instructions in order to minimize any setup errors. Note that this tutorial is based on the vtvt_tsmc180 library.

1. Analyze and Compile

2. Execute Simulate

3. Check the result waveform