Synopsys Tutorial

Power Estimation at the Gate Level
Using Power Compiler

Authors: Jinsik Yun, Jeannette Djigbenou, Dr. Dong S. Ha

Frequently Asked Questions

This tutorial shows a power estimation using Power Compiler. This tutorial targets Verilog designs. You have to follow these instructions in order to minimize any setup errors. Note that this tutorial is based on the vtvt_tsmc180 library.

Using Design Compiler, you first need to generate a forward saif file. Then include the forward saif file in your testbench to generate a backward annotated saif file. Finally, read the backward saif file back to perform the power estimation.

1. Generate a forward saif file

2. Generate a backward saif file

3. Generate power estimation report