Cadence Tutorial

Import Synthesized Design Into Cadence Composer Schematic View

 Author:  Jeannette Djigbenou

Once you have the synthesized schematic design saved as a verilog file, you may need to verify that the place-and-route tools have properly displayed the design. You can verify this by:

o         Importing the place-and-route layout to Cadence Virtuoso

o         Importing the Verilog netlist into a schematic in Cadence Composer

o         Running LVS on both views to verify that they have the same netlist.


This tutorial describes how you may import the synthesized netlist into a Cadence Composer Schematic view. To run this tutorial, you need a verilog netlist from the synthesized design. To learn how to get the verilog netlist, please refer to the appropriate instructions.


These steps describe how to import the synthesized design into Cadence Composer.

    • Make a new directory cad_test
    • Setup directory cad_test to run Cadence icfb
    • Add our standard cell library vtvt_tsmc250 into the cadence run directory cad_test.
    • Copy the synthesized verilog netlist into cad_test directory
    • Start Cadence icfb
    • In the CIW, go to File->Import->Verilog...
    • Fill in the VerilogIn form as shown below. Figure 1 displays the form.

o  Target Library Name: top_count_design.
Name of a library you wish the new schematic to be created in. This library does not need to exist prior to the run. It will be automatically generated. It is recommended to either create a new library for each run (if the design name is the same) or to delete any previous cells from previous runs. The new schematic cells fail to get updated sometimes.

o  Reference library: vtvt_tsmc250 basic
Symbol views are included in library vtvt_tsmc250. Pins are included in library basic. All cells mentioned in the verilog synthesized design will be chosen from the standard cell library.

o  Verilog Files to Import: syn_top_count.v
Enter the name of the verilog synthesized file you saved from synthesis.

o  Import Structural Modules As: Schematic.
This is the default value.

o  Power Net Name: vdd

o  Ground Net Name: vss

o  Keep everything else as default


Figure 1: VerilogIn Form

    • Click OK
    • A pop-up message will indicate that Verilog In import completed
    • The target library top_count_design is created and contains the names of modules imported from the verilog netlist. Select cell TOP_COUNT schematic as shown on Figure 2


Figure 2: Schematic View of TOP_COUNT design


    • In the schematic view of cell TOP_COUNT, you may descend into the hierarchy to view components of sub-modules. To descend into a cell, select the cell, go to Design->Hierarchy->Descend Read...The view of the sub-module will be displayed in Read-mode as shown below.

Figure 3: Sub-Module of TOP_COUNT

    • Within the sub-modules schematic view, you may descend, into each symbol to view the actual transistor-level schematic of each component.


To go to the next step in the ASIC design flow, you may use this synthesized schematic to verify with LVS that this schematic from the synthesized design and the layout from Place-and-Route match. Refer to the Cadence Tutorial section of our site for instructions to run LVS.