Research Projects

There are major on-going research projects as described below. The major sponsors of the research projects include Advantest Laboratories, Ltd., Bell Labs of Lucent Technologies, Electronics and Telecommunications Research Institute (ETRI), National Aeronautics and Space Administration (NASA), the National Science Foundation, Samsung Electronics, Virginia Tech Institute for Critical Technology and Applied Science (ICTAS), and Virginia Tech ASPIRES program.

On-orbit Health Monitoring and Repair Assessment of Thermal Protection Systems

Sponsor: National Aeronautics and Space Administration (NASA)
Participating Researcher: Jina Kim

On-orbit health MoNItoring and repair assessment of THERMal protection systems (OMNI_THERM) features impedance-based Structural Health Monitoring (SHM) and uses miniaturized autonomous sensor/actuators to diagnose damage and verify repair efficacy. Potential commercial applications include homeland security structural analysis to mitigate threats and assess damage, smart structures, and SHM of nuclear plants, aircraft, dams, and bridges.

A Prototype Structural Health Monitoring System

We created a fully self-contained prototype, and demonstrated SHM and repair assessment on Thermal Protection Systems (TPS). We have built the first integrated system that performs a complete, impedance-based SHM measurement and analysis process. We plan to evolve our hardware development focusing on lower power consumption, further miniaturization, environmental robustness, and scaling to multiple sensors. This project is in collaboration with Center for Intelligent Material Systems and Structures (CIMSS, directed by Prof. Daniel Inman) at Virginia Tech and Extreme Diagnostics, Inc.

Cell Libraries to Support VLSI Research and Education

Sponsor: National Science Foundation
Participating Researcher: Jeannette Djigbenou

Cell-based, VLSI design — the most widely used approach in today’s system-on-a-chip design — relies on a building-block infrastructure with standard cell libraries. All aspects of VLSI benefit from standard cell libraries, including full custom design, automatic layout generation, physical design, logic synthesis, CAD tools, and testing. We have been developing and distributing a standard-cell library targeting the TSMC-0.25um, 2.5-volt CMOS process available via MOSIS, along with CAD tools for testing and the source code. The library has been used by more than 280 universities worldwide.

D flip-flop Distributed by VTVT

Commercial library cells are the supplier’s proprietary information, and understandably, suppliers usually impose certain restrictions on the access and use of their library cells. Those restrictions on commercial library cells severely hamper VLSI research and teaching activities of academia. The project aims to address the problem. So researchers with academia can freely exchange their designs utilizing those library cells. Planned improvements include development of library cells for other processing technologies (such as IBM 0.13 um, TSMC 0.18 um, TSMC 0.35 um, and AMI 0.5 um); development of RAM and ROM compilers and data converters; and provision of additional features and simulation libraries.

Secure RFID with Ultra-Wideband Modulation

Sponsor: Discretionary Funding of the VTVT Group
Participating Researcher: Vipul Chawla and Shen Wang

Security in passive RFID is a major concern, and its implementation is highly challenging due to extreme low power constraints of a passive tag. Current passive RFID uses digital cryptographic algorithms like hashes and block cipher to secure tag-reader communication. However, these techniques suffer from problems like long system latency, high power consumption, and large tag silicon area. To address these weaknesses, we proposed a new approach for secure passive RFID. The proposed RFID tag employs impulse UWB communication for data uplink. The communication is secured by using a time-hopped pulse-position modulation (TH-PPM), in which the hoping sequence is known only to the reader and the tag. By adopting the hopping sequence as a secret parameter for the UWB communication link, eavesdropping of the communication is extremely difficult. Thus this technique avoids digital cryptography and supports privacy directly at the physical-communication layer. Also, TH-UWN outperforms narrowband communication, employed in current RFID systems, some of the important advantages are:

Difficult to eavesdrop
Increased communication reliability
Decreased system latency

Proposed Secure UWB RFID System

The goal of this research is develop the proposed RFID tag, and we investigate system model and design of such an RFID tag, channel model, UWB transmitter, pulse-position modulator, and pseudo random sequence generator. The tag is being designed to operate in the standard ISM 900 MHz UHF frequency band.

Ubiquitous Access of Internal Nodes for Test and System Diagnosis

Sponsor: Semiconductor Research Corporation (SRC) - Intel Custom Funding
Participating Researcher: Rajesh Thirugnanam

The number of pins on a VLSI chip grows with the higher level of integration through advancement of VLSI technology into deeper submicron. The increasing pin count results not only from additional signal pins, but also from additional power and ground pins. On the silicon chip itself, a power distribution network (PDN) connects the power pins of the package and distributes power across the chip, i.e., a power line is in proximity to any internal node. This offers the possibility of sending control signals to any internal node through power pins and the PDN or monitoring any internal nodes, which is a highly attractive feature for testing and diagnosis. A key roadblock on the use of power pins and PDNs is that power pins combined with decoupling capacitors form a low pass filter to suppress high frequency signals.


Measurement Setup

Our initial research findings show that, in fact, such power pins fail to behave as a low pass filter at a high frequency band over 1 GHz due to parasitics associated with the package and low self resonant frequencies of decoupling capacitors. We investigate wireless communications techniques, specifically UWB (ultra wideband) and CDMA (code division multiple access), to use power pins and PDNs for testing and diagnosis of microprocessors. Our research activities include accurate high frequency modeling of PDNs, channel modeling, optimal modulation strategy, spreading codes and low noise data recovery block design.

Power Efficient Buck Converters through Digital Control

Sponsor: National Science Foundation (through CPES)
Participating Researcher: Na Kong

Recently, buck converters draw good attention in low power ASICs, ambient energy harvest systems, and mobile applications besides its traditional power electronics systems. Traditional buck converters rely on analog controls. The digital control approach offers potentially several advantages such as the immunity to component variations, digital communication capability, few external components, the ability to perform sophisticated control algorithms and self-calibrations, faster IC design using HDL synthesis and controller adaptation.


A Prototype Buck Converter with a Digital Controller

Although it is well accepted that digital control is more advantageous than its counterpart analog control, existing digital control architectures are still based on analog architectures such that one or two ADCs followed by a compensator and a DPWM (Digital Pulse Width Modulation). Therefore, existing digital architectures may fail to exploit the full potential of digital control. The objective of this research is to investigate full capability of digital control under a new design paradigm of digital circuit design and digital signal processing, while imparting from the traditional analog design concept. Toward the objective, we are developing a simulation platform which can model building blocks of a system at various levels. The platform will be used to estimate the performance and to design a digital control chip ultimately. The project is in collaboration with Center for Power Electronics Systems (CPES) of Virginia Tech.