Synopsys Tutorial

Power Estimation at the Gate Level using
Primetime-PX or Power Compiler

Author: Jeannette Djigbenou

Frequently Asked Questions

This tutorial shows how to get power estimation at the gate level through logic simulation with test vectors supplied by users for a 4-bit counter, which is described in the behavioral level, using Primetime-PX or Power Compiler. First, you will synthesize it, and then you can derive the power estimation of the synthesized circuit. Note that through this procedure, you also can get the area and timing slack estimation. This tutorial targets VHDL designs.

Using Design Compiler, you first need to generate a forward saif file. Then include the forward saif file in your testbench to generate a backward annotated saif file. Finally, read the backward saif file back to perform the power estimation. You must set up your Synopsys environment prior to running this tutorial.

  1. Download a 4-bit counter example into your working directory and its testbench. Since VHDL reader is case insensitive while other tools that will be used in this tutorial are case sensitive, you will need to make sure all your VHDL files are in uppercase. In case you did not do so, there is no need to panick :). Run the following command once you are complete writing your VHDL files. This perl command line will automatically convert all your file into uppercase. Since VHDL is case insensitive, your design remains equivalent.
    Command to convert file to uppercase letters: perl -pi.bak -e "tr/a-z/A-Z/" <filename> . The <filename>.bak file is the original file you created.
  1. Create subdirectory named 'work' under your current directory if it does not already exist. All intermediate files will be stored under this directory.

  2. Verify that your design environment is properly set to save and re-simulate a synthesized design in vhdl format. Check the following in your settings before you proceed:
    • In file .synopsys_dc.setup, verify that the packages in the vhdlout_use_packages are seperated by just one space.
      For example, set vhdlout_use_packages {IEEE.std_logic_1164 IEEE.std_logic_arith IEEE.std_logic_textio vtvt_tsmc180.components}
    • In file .synopsys_vss.setup, verify that this line exists: vtvt_tsmc250: ./vtvt_tsmc250 (or vtvt_tsmc180: ./vtvt_tsmc180 if you're using the TSMC .18um library)
  1. Generate a forward saif file for your design. Refer to the script cnt_fw.scr
    • Type dc_shell-xg-t in UNIX prompt. Design Compiler starts.
    • Type source cnt_fw.scr at the DC Shell prompt.
    • The VHDL synthesized design cnt_syn.vhd and the saif file cnt_fw.saif of the counter are generated.
      • Note: in case you are using your own files, you have to modify the script file “cnt_fw.scr” according to your own design file names. That applies for all the script files being used in this tutorial.

  2. Analyze your synthesized design
    • vhdlan cnt_syn.vhd
    • vhdlan tb_cnt_bhv.vhd

  3. Generate a backward saif file recording toggle information
    • Compile and elaborate your design, and set your simulation environment to call UCLI (Unified Command Line Interface) to run VHDL SAIF commands.
      scs work.CFG_TB_CNT_BHV -debug
      scsim -ucli
    • The ucli prompt appears. You may now generate the backward SAIF file or the VCD file to get power estimation. If you intend to use Power Compiler, you will need the SAIF for power estimation. If you intend to use Primetime-PX, you either need the VCD or SAIF file.
      • Option1: Generate the SAIF file directly. Refer to the script cnt_bw_gen_saif.scr
        • Type source cnt_bw_gen_saif.scr
        • The backward saif file is generated: cnt_bw1.saif
      • Option 2: Dump VPD file, then generate VCD and SAIF file. Refer to the script cnt_bw_gen_vpd.scr
        • Type source cnt_bw_gen_vpd.scr
        • The VPD file is generated: cnt_vpd.vpd
        • Convert the VPD file into VCD then SAIF files by typing the following commands:
          • vpd2vcd cnt_vpd.vpd cnt_vcd.vcd
          • vcd2saif -input cnt_vcd.vcd -output cnt_bw2.saif -32 -format VHDL
          • The backward saif file is generated: cnt_bw2.saif

  4. Synthesis of behavioral model with input toggle information. Get the power estimation for your design with either Primetime-PX or Power Compiler. The two methods are described below:
    1. Using Primetime-PX: Refer to the script cnt_power_pt_shell.scr
      • Type pt_shell in UNIX prompt. Primetime-PX starts.
      • Type source cnt_power_pt_shell.scr at the PT Shell prompt.
      • Power report is generated: power_toggle_pt_shell.rpt, the power unit is in uWatts
      • For the area report, the unit is in µm^2. So, to get the area in terms of gate count, the total area should be divided by the area of the NAND2 gate in either our vtvt_tsmc250.lib. or vtvt_tsmc180.lib library file. The table below summarizes the values for the NAND2 gate area in the 'lib'files.

        NAND2 Gate  Area

        vtvt_tsmc250.lib

        vtvt_tsmc180.lib

        65.3184

        36.7416



    2. Using Power Compiler: Refer to the script cnt_power_dc_shell.scr
    • Type dc_shell-xg-t in UNIX prompt. Design Compiler starts.
    • Type source cnt_power_dc_shell.scr at the DC Shell prompt.
    • Power report is generated: power_toggle_dc_shell.rpt, the power unit is in uWatts
    • For the area report, the unit is in µm^2. So, to get the area in terms of gate count, the total area should be divided by the area of the NAND2 gate in either our vtvt_tsmc250.lib. or vtvt_tsmc180.lib library files. Again use the values stated in the above table.
      • If you have a different module's report not your target module(in this tutorial "updown_counter" like the below, please refer to FAQ section

        power report error