Synopsys Tutorial

Design Vision: A Logic Synthesis Tool

Author: Jinsik Yun, Jeannette Djigbenou, Dr. Dong S.Ha

Frequently Asked Questions

This tutorial describes how to use Synopsys Synthesis tool, Design Vision, to generate a synthesized netlist of a design. To run this tutorial, you need a VHDL file which contains a behavioral description of the project you intend to design. Prior to this tutorial, it is recommended that you verify the logic of your design. To learn how to run logic simulation, please refer to the Logic Simulation Tutorial.

This tutorial shows a logic synthesis process for a 4-bit counter, which is described in the behavioral level. You must have setup your unix environment before this!!!

If you are using the standard cell libraries release package, start Synopsys using the Synopsys_Libraries directory of the release package. For directions on how to start Synopsys with the release package, please refer to the Synopsys Installation tutorial.

Copy an example of a 4-bit counter and a test bench for the counter into your working directory.

Wasn’t that FUN!!!