Synopsys Tutorial

Design Vision - Verilog Logic Synthesis Tool

Authors: Jinsik Yun, Dr. Dong S. Ha


Frequntly Asked Questions

This tutorial shows a Verilog synthesis process using Design Vision. After that, it will show simulation methos for synthesized netlist. You have to follow these instructions in order to minimize any setup errors. Note that this tutorial is based on the vtvt_tsmc180 library.

1. Synthesis for generic gates

2. Synthesis for vtvt_tsmc_library

3. Extract Netlist

4. Simulating a Synthesized Netlist

5. Design Compiler shell and Optimizing the clock skew