Cadence Tutorial

Logic Simulation with Verilog

Authors: Jeannette Djigbenou and Jia Fei

This tutorial shows how to perform logic simulation using Verilog. The procedure is for a quick and simple solution, and it does not explore full feature of Verilog. The example to be used in this tutorial is a 2x1 multiplexer. At this point, you should have set up the environment. Otherwise, refer to Setting Up Your Unix Environment.

If you don't have any of them, refer to previous sections, Gate-Level Schematic Entry with Composer for the gate-level schematic and Switch-Level Schematic Entry with Composer for the switch-level schematic.


file -> open ...
A new window appears. Set the following items, and click OK.

Tools -> Simulation -> Verilog-XL
A new window appears. Verify Run Directory is "My_Mux.run1", and click OK.

Stimulus -> STL -> Edit Stimulus...

Edit STL windows appear. Check "Compile STL after Editing?", and click OK.

the line xv(0 0 0). This line means the first stimulus vector is (0 0 0) for the inputs defined in the top part of the file. Add other stimulus vectors. For the 2x1 multiplexer with three inputs, enter the following vectors.
xv(0 0 0)
xv(0 0 1)
xv(0 1 0)
xv(1 1 1)
Save the file.

Have fun!