Cadence Tutorial

Inverter Tutorial with Virtuoso

 Authors: Jeannette Djigbenou, Meenatchi Jagasivamani, Jos Sulistyo


This tutorial shows layout of a CMOS inverter.  At this point, you should have set up the environment.  Otherwise, refer to Setting UP Your Unix Environment. You are assumed to know how to use layout editor, Virtuoso. If you don't know the layout editor, follow the on-line tutorial in the cdsdoc.  To start up open book, type cdsdoc & from a terminal.  The tutorial for Virtuoso can be found in cdsdoc at:  Custom IC Layout -> Layout -> Cell Design Tutorial -> Chapter 2.

The tutorial given below is for the NCSU design kits:


       TSMC 0.25um (MOSIS deep-submicron rule) of NCSU Kit


In the Command Interface Window (CIW):

a)  Select File -> New -> Cellview.
b)  Choose the library under which you would like to create the new cell view.
c)  Enter Cell Name:  My_Inv  (for the tutorial)
d)  Choose Virtuoso as the Tool.  View name should be layout.
e)  Click OK.
A blank virtuoso window should open.

a)  Options -> Display.
b)  Set the following options:


Use this figure as a guideline as you go through the procedure.


 In this tutorial, we are using the Nwell process.  Thus, the substrate will be p-substrate.  We will create a pmos transistor first.  To do that we need an Nwell in which the pmos transistor will be formed.

a) Select the n-well layer from the LSW window
b) Select the Create->Rectangle (or choose the Rectangle icon from the side toolbar).
c) Using your mouse, draw the n-well on the cellview to be 2.94 wide by 2.52 tall .

a) Select the pselect layer from the LSW window; we will draw the pselect enclosing the transistor
b) Select the Create->Rectangle (or choose the Rectangle icon from the side toolbar).
c) Using your mouse, draw the pselect on the cellview;  1.98 wide and 0.96 tall; its left- and right-edges should be 0.48 away from well edges.
The pselect should be placed within the n-well, even if the size should vary. (you can use the Edit->move command to move the layer)

a) Select the pactive layer from the LSW window; we will draw the active region of the p-device
b) Select the Create->Rectangle (or choose the Rectangle icon from the side toolbar).
c) Using your mouse, draw the pactive on the cellview to be 1.5 wide by 0.48 tall - it should be enclosed by the pselect by 0.24 and by the nwell by at least 0.72

a) Select the poly layer from the LSW window
b) Select the Create->Rectangle (or choose the Rectangle icon from the side toolbar).
c) Using your mouse, draw the poly on the cellview to be 0.24 long by 1.32 wide.
The poly should be placed at the center of the p-island.  The poly should extend over the p-island by 0.30 um.

a) Select the contact layer from the LSW window
b) Select the Create->Rectangle (or choose the Rectangle icon from the side toolbar).
c) Using your mouse, draw the contact on the cellview to be 0.24 long by 0.24 wide.
The contact should be placed at both sides of the pactive.  Repeat the above process for the second contact.

a) Select the nselect layer from the LSW window
b) Select the Create->Rectangle (or choose the Rectangle icon from the side toolbar).
c) Using your mouse, draw the nselect on the cellview to be 1.98 wide by 0.92 tall

a) Select the nactive layer from the LSW window
b) Select the Create->Rectangle (or choose the Rectangle icon from the side toolbar).
c) Using your mouse, draw the nactive on the cellview to be 1.50 wide by 0.48 tall; it should be enclosed by the nselect by 0.24 around its edges. Also, it needs to be at least 0.72 away from the n-well (= 6 x lambda; MOSIS rule 2.3 for DEEP).

a) Extend the poly layer created for the p-transistor over the n-island, making sure that the poly extension over n-island is 0.30.  (you can use the Edit->Stretch command to stretch the poly)
The poly should be placed at the center of the n-island.

a) Select the contact layer from the LSW window
b) Select the Create->Rectangle (or choose the Rectangle icon from the side toolbar).
c) Using your mouse, draw the contact on the cellview to be 0.24 long by 0.24 wide.
The contact should be placed at both sides of the p-island.  Repeat the above process for the second contact.

a) Select the nselect layer from the LSW window; we will draw the nselect enclosing the substrate (vdd) contact for the P transistor.
b) Select the Create->Rectangle (or choose the Rectangle icon from the side toolbar).
c) Using the mouse, draw the nselect on the cellview; at least 0.96 tall and wide, as it will have to enclose the contact n-active by at least 0.24, which in turn enclose the contact by at least 0.12.
The nselect abuts directly to the pselect of the P transistor, but they should not overlap. Also, both selects should be placed within the n-well.
d) Select the nactive layer from the LSW window; we will draw the body contact region of the p device.
e) Select the Create->Rectangle (or choose the Rectangle icon from the side toolbar).
f) Using your mouse, draw the nactive on the cellview to be at least 0.48 wide by 0.48 tall
g) Add a contact in the center of the well-contact island.

a) Select the pselect layer from the LSW window; we will draw the nselect enclosing the substrate (vss = ground) contact for the N transistor
b) Select the Create->Rectangle (or choose the Rectangle icon from the side toolbar).
c) Using the mouse, draw the pselect on the cellview; at least 0.96 tall and wide, as it will have to enclose the contact p-active by at least 0.24, which in turn enclose the contact by at least 0.12.
The nselect abuts directly to the nselect of the N transistor, but they should not overlap.
d) Select the pactive layer from the LSW window
e) Select the Create->Rectangle (or choose the Rectangle icon from the side toolbar).
f) Using your mouse, draw the n-island on the cellview to be 0.48 wide by 0.48 tall; it must be enclosed by the pselect by 0.24.
The p-island should be placed at least 0.48 um (= 4 x lambda, MOSIS rule 2.5 DEEP) below the n-transistor.
g) Add contacts in the center of the substrate-contact island.

a) Connect the source of p-transistor to the well-contact using the metal 1 layer.
b) Connect the source of n-transistor to the substrate-contact using the metal 1 layer.
c) Add a contact to the gate (poly)

At this point, your layout should look something like this.

You need to add pins for the input (named ip), output (named op), vdd, and vss in order to pass DRC.  Go to the Creating I/O Pins section to get the procedure on how to add pins to your layout.

DRC is used to check that all process-specific design rules (such as spacing) have been met.  Go to the DRC section to get the DRC procedure.

This concludes the Inverter tutorial.  Back to Top