• Overview
• Design Flow
• Tutorials
  • Overview
  • Cadence
    • Circuit Design
      • Analog
      • Digital
      • Mixed-Signal
    • Layout
  • Synopsys
  • Hspice
  • SystemC
• Cell Libraries
  • Overview
  • Request
  • Download
  • Guidelines
  • Users
  • Contact
• CAD Tools
  • Overview
  • Request
  • Download
  • Users
  • Contact
• Links

• Layout with Virtuoso


• Inverter Tutorial with Virtuoso
• Capacitor and Resistor Layout
• FAQ about Layout
• Introduction to SKILL


• DRC (Design Rule Check) with Virtuoso


• LVS (Layout-Versus-Schematic) with Virtuoso


• Logic Simulation with Verilog

Netlist Extraction with Cadence:

• HSpice Netlist Extraction with Cadence


• Spectre Netlist Extraction with Cadence
• Spectre Simulation with Command Line
• Spectre Simulation with Analog Artisit (Graphical Interface)


• SOC Encounter: Place and Route Tool


• Import Verilog Netlist into Schematic


• Import GDS into Cadence Layout


• Pad Insertion


• Steps for Chip Submission

Navigation

Cadence Tutorial

Steps for Chip Submission Authors:  Carrie Aust

---

1.  Create GDSII file for layout.

• Open Stream Out form from CIW window.  File->Export->Stream
• Fill in Library Name, Cell Name, and Output File boxes
• Include layer map in User Defined Data
• Click User Defined Data button in Stream Out form
• Enter the appropriate file name for the given technology in Layer Map box.
         If you are using NCSU design kit, you must use CIF output format.
• Click ok.
• Click ok.
• You should get a message stating stream out was successful.  The GDSII output file is the file you used in the Output File box.

2.  Or Create CIF file for layout

• Open CIF Out form from CIW window. File->Export->CIF.
• Follow all steps from 1.  The layer map table is $CDK_DIR/local/pipo/cifOutLayerMap (for the NCSU Kit) with CDK_DIR being the installation path to the kit.

3.  Find checksum for output file (GDSII or CIF)

• Retrieve mosiscrc.c from MOSIS web-site at http://www.mosis.org/Customer/Email/mosiscrc.c
• Compile the c language file.

>>gcc mosiscrc.c

• Use executable to find checksum of file.  Record the two numbers that are given.  For more information see the MOSIS web page http://www.mosis.org/Customer/Email/email-system.html

• For GDSII

          >>a.out -b <GDSII file name>

• For CIF

          >>a.out -t <CIF file name>

4.  Submitting the Chip....

Use the one-step submission form to submit the chip to MOSIS for fabrication.  Refer to http://www.mosis.org/Customer/Email/email-templates.html#one-step for details.  The lambda and the technology code are specific to the process your are using.  The technology codes and lambda values are found at http://www.mosis.org/Technical/Techcodes/menu-techcodes.html

If you are using the NCSU design kit, the technology code is specific to the kind of devices you are using. All the SCMOS options are given at http://www.mosis.org/Technical/Designrules/scmos/scmos-main.html The options available are specific to the process (see http://www.mosis.org/Technical/Processes/menu-processes.html )The lambda values are given for each of the processes.