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• Layout with Virtuoso


• Inverter Tutorial with Virtuoso
• Capacitor and Resistor Layout
• FAQ about Layout
• Introduction to SKILL


• DRC (Design Rule Check) with Virtuoso


• LVS (Layout-Versus-Schematic) with Virtuoso


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Netlist Extraction with Cadence:

• HSpice Netlist Extraction with Cadence


• Spectre Netlist Extraction with Cadence
• Spectre Simulation with Command Line
• Spectre Simulation with Analog Artisit (Graphical Interface)


• SOC Encounter: Place and Route Tool


• Import Verilog Netlist into Schematic


• Import GDS into Cadence Layout


• Pad Insertion


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Cadence Tutorial

Spectre Netlist Extraction with Cadence

Authors: David Donofrio, Jos Sulistyo, Meenatchi Jagasivamani and Carrie Aust

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This tutorial explains how to extract a Spectre netlist from your cellview from either the schematic or layout view.

• From Virtuoso (the layout view):

a) Get the extracted view of the layout:

1. Select Verify -> Extract.
2. To extract resistances and capacitances for NCSU kit:
1. Click the Set Switches button.
2. Select Extract_parasitic_caps, Extract_cap, and Extract_resistor option. Note that Extract_cap (extracts intentional, non-parasitic capacitors) and Extract_parasitic_caps are not the same option.
3. In the CIW, type "NCSU_parasiticCapIgnoreThreshold=x" with x being the maximum value of parasitic capacitance to ignore (in Farads) - 1e-18 is a typical value.
4. Leave all other options as default.
5. Click OK.
3. Click OK.

b) Start Analog Artist: Select Tools -> Analog Environment from the extracted window.

NOTE: By starting Analog Artist from Composer the current extracted layout will automatically be used as the target design

c) Go to Spectre Netlist Simulation Procedure.

• From Composer (the schematic view):

a)Once the schematic is complete, place pins (Add->Pin . . . or 'p' shortcut) on signals you wish to name

These are the signals that you will later be able to easily plot and stimulate.
Designate pin to be input, output or input/output (recommended for Vdd and Vss)

a) Choose Design-> Check and Save from the schematic window
b) Start Analog Artist: Select Tools -> Analog Environment from the schematic window.

NOTE: By starting Analog Artist from Composer the current schematic will automatically be used as the target design

c) Go to Spectre Netlist Simulation Procedure.

• NOTE:When using both switch-level and gate-level logic in a schematic
1. Extract standard cells corresponding to the gates in your schematic

a) Open the extracted view of a standard cell in Cadence Virtuoso.
b) Follow instructions for extraction from layout given in the Netlist Extraction Procedure below. The HSPICE netlist is the subcircuit definition of the corresponding gate. (Ex: wand2_2.sp)

2. Extract schematic for Netlist using instructions given in the Netlist Extraction Procedure below.
3. Include the subcircuit definition in the top-level circuit HSPICE file using a .include statement. (Ex: ?.include ?./wand2_2.sp??)