Cadence Tutorial
Place
And Route Using Cadence SOC Encounter
Author:
Jeannette Djigbenou
In this tutorial we are using the Cadence's
SOC Encounter version 5.2 (First Encounter v05.20-p002_1 9 (32 bits)) and
running on x86_64 w/Linux 2.6.9-42.0.2.ELsmp machine.
After synthesizing your design, the synthesized
netlist was saved in the verilog format as syn_top_count.v. You may need to
"convert" this synthesized design into a layout. For this purpose, Cadence SOC
Encounter is a place-and-route tool that uses a verilog netlist and generates its
equivalent layout view.
This tutorial describes how to use
Cadence SOC Encounter to generate a layout view of the synthesized design,
using vtvt_tsmc250 standard cells library.
1. Before you start
A few files and
directories are necessary for a successful run of SOC encounter. These files
are available in the standard cell library package.
o Technology file: vtvt_tsmc250.lib (in
Synopsys_Libraries directory)
o LEF file of the library:
vtvt_tsmc250.lef (in directory vtvt_tsmc250_lef)
o Verilog netlist: syn_top_count.v. This
file is the verilog netlist of the synthesized design. (in directory
tutorial_files)
o GDS2 Map vtvt_SoCE2df2.map (in directory
vtvt_tsmc250_lef)
o Optional Files:
- DEF File: If you wish to place
I/O pads on the design. We are not using pads in this tutorial
- Time Constraints file: If you
wish to insert time constraints from Design Compiler. This file is
generated during synthesis. We are not using this file in this tutorial.
2. Start SOC Encounter
To start SOC
encounter, make a directory soc_enc which contains the following files:
o Technology file: vtvt_tsmc250.lib
o LEF file of the library:
vtvt_tsmc250.lef
o Verilog netlist: syn_top_count.v
Then, in
directory soc_enc, start SOC Encounter:
.../soc_enc>Cadence
[Cadence].../soc_enc>encounter
3. DESIGN->DESIGN IMPORT
Within the
GUI, go to Design-> Design Import.
Fill out the
Basic and Advanced tabs as follow:
Advanced
Tab->Power
o
Power
Nets: vdd
o
Ground
Nets: vss
Basic Tab:
o
Verilog
Netlist: syn_top_count.v.
The verilog file from the synthesized design.
o
Top
Cell: TOP_COUNT
Name of the main module of the verilog file.
o
Timing
Libraries: Common Timing Libraries: vtvt_tsmc250.lib
o
LEF
Files: vtvt_tsmc250.lef
o
Click
OK. You may also save the configuration for future purposes.
Leave all
other fields as default.
Figure 1: Design Import
4. FLOORPLANNING->SPECIFY FLOORPLAN
Go to
Floorplan->Specify Floorplan. Specifying the Floorplan depends on the size
of the design. You may follow the following settings or chose your own values.
Fill out the
form as shown below:
Design
Dimensions:
Size
by Die->Size by: Width and Height:
Die
Width: 500
Die
Height: 500
Core Margins by -> Core to IO
Boundary
Core to Left: 38
Core to Top: 38
Core to Right: 38
Core to Bottom: 38
Figure 2: Specify Floorplan
Figure 3: After Floorplan
5. POWER->POWER PLANNING-> ADD RINGS
Go to Power->Power
Planning->Add Rings.
Fill out only
the Basic tab.
Ring
Configuration:
Metal1 and Metal 2 Width: 10.8
Metal1 and Metal2 Spacing: 2.16
Leave all
other fields as default.
Select OK.
Figure 4: Add Rings
Figure 5: After Adding Rings
6. POWER->POWER PLANNING-> ADD STRIPES
Go to
Power->Power Planning->Add Stripes and fill out the form as follow.
Set
Configuration:
Layer: Metal2
Direction: Vertical
Width: 10.8 (same as step 5)
Spacing: 2.16 (same as step 5)
Leave all
other fields as default.
Select OK.
Figure 6: Add Stripes
Figure 7: After Adding Stripes
7. ROUTE->SPECIAL ROUTE
Go to
Route->
Select OK.
Figure 8: After SRoute
8. PLACE->STANDARD CELLS AND BLOCKS
Go to
Place->Standard Cells and Blocks and fill out the form as follow. Select Run
Timing Driven. Leave all other fields as default.
Make sure the
View option is set to Physical view and not Floorplan view. This could be
resolved by selecting the appropriate view option located on the upper right
side of the window.
Figure 9: Place Standard Cells Form
Figure 10: After Placing Cells
9. ROUTE->NANOROUTE
For the
Global routing process, use Nanoroute and select the Timing Driven Option.
Leave
everything else as default. Select OK. This step may take some time, based on
the size of your design.
Figure 11: Nanoroute Form
Figure 12: After Routing Nanoroute
10. PLACE->FILLER->ADD...
Add filler cells
in the design to allow all the wells to be at the same potential.
Figure 13: Adding Filler cells
11. VERIFY FINAL LAYOUT
- Go to Verify-> Verify
Connectivity: You may keep the default settings.
The design
should pass connectivity.
- Go to Verify -> Verify
Geometry. Verify geometry with the default settings.
The design
should pass this test as well.
However, if
you are using pads, you might get some shorts errors. You may resolve these
errors by moving the place-and-route layout to Cadence Virtuoso and updating
the routing to pass DRC.
12. EXPORT GDS...
Export its
GDS file.
Go to
Design->Save->GDS...
Fill out the
form as follow:
- Output Stream File: TOP_COUNT.gds
The name of the GDS file you wish to save. - Map File: vtvt_SoCE2df2.map
This map file is used to map layer from SOC Encounter into df2.
Figure 14: GDS Export Form
13. SAVE AND EXIT
You have
completed this tutorial. Save the design by going to Design->Save Design.
Wish to move
to the next step of the ASIC design flow? Then, import the GDS file into
Cadence Virtuoso.
Next Page