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• Inverter Tutorial with Virtuoso
• Capacitor and Resistor Layout
• FAQ about Layout
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Cadence Tutorial

Capacitor and Resistor Layout

Authors: Jeannette Djigbenou, Jos Sulistyo

This tutorial shows layout of capacitor and resistor. At this point, you should have set up the environment and successfully completed the inverter tutorial or otherwise know how to do layout using Virtuoso. If you have not set up your UNIX environment, refer to Setting UP Your Unix Environment. You are assumed to know how to use layout editor, Virtuoso. If you don't know the layout editor, follow the on-line tutorial in the cdsdoc. To start up open book, type cdsdoc & from a terminal. The tutorial for Virtuoso can be found in cdsdoc at: Custom IC Layout -> Layout -> Cell Design Tutorial -> Chapter 2. The inverter tutorial is also recommended.

Note that this documentation is not presently intended for showing how to create good layouts (e.g., low-parasitic capacitance resistors, neat looking layouts, or whatever); it is only intended for showing what resistors and capacitors look like.

The layers needed to draw analog elements such as resistor or capacitor is kit- and technology-dependent. At this point, the tutorial given below is only for:

• TSMC 0.25um (MOSIS deep submicron rule) of NCSU kit (NCSU_TechLib_TSMC03d)

TSMC 0.25um (MOSIS deep-submicron rule) of NCSU kit

• Example Layouts:

a) It is assumed that you do not already have directories or libraries named cap_res_sample.
b) Download this Cadence layout library to your working directory.
c) Untar the file.
/usr/local/bin/tar zxvf cap_res_sample.tz
d) Add the entry for the new library to your cds.lib. Add the following line to cds.lib:
DEFINE cap_res_sample ./cap_res_sample

• Explanations for Resistor Layout:

a) This is the jpg image. However, from icfb/Virtuoso you would be able to examine it more closely.
b) The resistor is made by enclosing poly with sblock (the NCSU kit name for silicide block).
c) Poly resistance is only about 200 Ohm/square. This sample is only 1.786 k. See extracted view.

• Explanations for Capacitor Layout:

a) This is the jpg image. However, you would be able to examine it more closely from icfb/Virtuoso.
b) This is a cap_top_metal capacitor (see purple areas)
c) The cap_top_metal area defines the capacitor area. It comprises the upper plate.
d) The lower plate is metal4 (yellow), upper contact - not upper plate - is metal5(light blue blue)
e) The lower plate must overlap the upper plate by 0.6um. The upper plate must be at least 6x6 um^2.
f) That metal5, along with via4 (small deep blue dots), connects the two plates.
This is a jpg snapshot of the contacts.
g) This 27.6 x 27.6 um^2 capacitor is only about 762 fF. See extracted view.

• Note on creating the "extracted" view. To obtain resistors / capacitors, when doing Verify -> Extract in layout window, add the Extract_resistor and Extract_cap switches, among others (you may like to add Extract_parasitic_cap, among others, which is not the same as Extract_cap). See also the tutorial page on HSPICE Netlist Extraction.
• For further info on layout, see MOSIS design rules website, particularly design rules on drawing silicide block for resistor, and on drawing capacitors. Note, however, that sometimes the NCSU kit has its own, more restrictive rules.

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