Cadence Tutorial

Pad Insertion

 Author:  Jeannette Djigbenou


Once your synthesized design has passed physical verification and power estimation, you can insert pads to the design for fabrication. Pads usually are depending on the fab that you will be sending your information to. In this tutorial, we are sending the design to Mosis. This tutorial describes how to insert pads to a design.

One way to insert pads would consist of modifying the synthesized verilog file by inserting the pad cells and re-running place-and-route with the dummy cells of the pads. These dummy cells are DRC clean, so your place and route design should be DRC clean. In this tutorial, we are using TSMC 0.25 pads available through MOSIS. If you are using another technology, please contact MOSIS to obtain the I/O pads for the corresponding technology.

Pad Insertion

The library Mosis_TSMC250 is created. You can view its content in Library Manager.

pad_insertion_3

pad_insertion_4

Now, you can submit the design to MOSIS. Follow the next tutorial for more details.

  • When you save gds file, please use vtvt_tsmc250_StreamIn.map file as your Layer Map Table
  • You can find the way how to save GDS from this tutorial: Chip Submission