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• Layout with Virtuoso


• Inverter Tutorial with Virtuoso
• Capacitor and Resistor Layout
• FAQ about Layout
• Introduction to SKILL


• DRC (Design Rule Check) with Virtuoso


• LVS (Layout-Versus-Schematic) with Virtuoso


• Logic Simulation with Verilog

Netlist Extraction with Cadence:

• HSpice Netlist Extraction with Cadence


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Cadence Tutorial

LVS (Layout-Versus-Schematic) with Virtuoso

 Authors:  Jeannette Djigbenou, Jia Fei, and Meenatchi Jagasivamani

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This tutorial shows how to perform layout-versus-schematic (LVS) check using a multiplexer.  At this point, you should have set up the environment. Otherwise, refer to Setting UP Your Unix Environment.

Before you start, you have to have a gate-level schematic diagram (view name: schematic) and a layout (view name: layout) of a multiplexer in MOSIS library. You also have to have a switch-level schematic diagram (view name: schematic) of every gate used in the gate level schematic diagram in MOSIS library.

If you don't have any of them, refer to previous sections, Schematic Entry with Composer , and Layout with Virtuoso for MOSIS Library for the layout.
 

1. Open the Schematic and Layout views.
• From the CIW:

a) Select File -> Open.
b) A new window appears.  Set the following items, and Click OK.

• Library Name: MOSIS
• Cell Name: My_Mux
• View Name: schematic

c) Select File -> Open.
d) A new window appears.  Set the following items, and Click OK.

• Library Name: MOSIS
• Cell Name: My_Mux
• View Name: layout

Case 1: If your design has transistor level schematic beneath the top level schematic, please follow the procedure below:

For your simulation to work properly, make sure you have specified the power nets (VDD, VSS, and GND).  It's case sensitive.  To find out the names the library uses for the power nets, look at any layout of the basic cell (e.x. had2) in the design kit you use. In this tutorial, we'll just call them VDD! and VSS!

1. By appending a wire label with a '!',the label becomes global.  This means that all wires in the entire design hierarchy labeled with this name are considered to be connected, even if they physically are not.

a)  To specify the power nets, type l and a pop up menu will appear.
b)  Type VDD! in the Names field.  Then move your cursor to the wire designated as VDD! and click on the left mouse button.
c)  Do the same for VSS!

2. If you have already added the pins for the power nets, but the name is not correct:

a)  Click on the pin
b)  Type q (properties) and a window will be pop up.
c)  Edit the properties of the pin by changing the pin name.

This step is very important, make sure you do it correctly. Otherwise, you will get a lot of errors when doing LVS although there is no error in you schematic or your layout!!

Case 2: If your schematic is at the gate level (no transistor level schematic beneath it), proceed to the next step.

The following steps are common for both gate level and transistor level schematics:

1.  Check and Save your design (schematic):

a)  Click on the first icon to the left of the schematic (it is the icon with a box and a check mark).

• You will be warned if you have any floating wires or pins.  You can also perform the same function by typing X or selecting Check and Save from the Design menu of the schematic window.
• Make sure you select Check and Save, not just Save.
1. From the Command Interface Window (CIW):

a) Select File -> Open.
b) A new window appears.  Set the following items, and Click OK.

• Library Name: MOSIS
• Cell Name: My_Mux
• View Name: layout

Make sure you have labeled the VDD! and VSS! pins for the power nets in layout.

• To do this select the Metal1 pn pattern which is just a rectangle outline with an X across.  To draw the labels, type Ctrl-P.  A pop up menu will appear.  Type VDD! for the Terminal Names field and select the I/O type as jumper.  Then move your cursor to the starting point of the label and click on the left mouse button.  Move your cursor to size the label and click on the left mouse button again.  Likewise, label the VSS! pin.
• If you have already specified another name for power nets, type q to change the pin name.
2. A Virtuoso window shows the layout of a multiplexer. Select Verify -> Extract.

• An extractor window appears. Click OK and watch any errors in CIW.

It extracts a netlist from the layout, and creates a new view name "extracted."

4. Open the multiplexer with view name "extracted". (Click Design -> Load ...)

A new window appears. Set the following items, and click OK.

• Library Name: MOSIS
• Cell Name: My_Mux
• View Name: extracted
4. A Virtuoso window shows the extracted view of the Inverter. Select Verify -> LVS ...

A new window appears. Set the following items under Schematic, and click "RUN." It takes for a while.

• Library Name: vtcells
• Cell Name: My_Mux
• View Name: schematic
• Run Directory: LVS
• LVS Option:  Rewiring, Device Fixing, Terminals
• Move Job Priority knob to 20.
5. To see if the job is still running, you can click on the Job Monitor... button and a pop up menu will appear.
6. After a while, a pop up menu will appear notifying you of the successful completion or failure of the LVS job. Click OK.
7. In the LVS window, click "Output" to get the information regarding the lvs run.
• If the netlist doesn't match, click" Error Display" to find out the error.

Have fun!