• Overview
• Design Flow
• Tutorials
  • Overview
  • Cadence
    • Circuit Design
      • Analog
      • Digital
      • Mixed-Signal
    • Layout
  • Synopsys
  • Hspice
  • SystemC
• Cell Libraries
  • Overview
  • Request
  • Download
  • Guidelines
  • Users
  • Contact
• CAD Tools
  • Overview
  • Request
  • Download
  • Users
  • Contact
• Links

• Layout with Virtuoso


• Inverter Tutorial with Virtuoso
• Capacitor and Resistor Layout
• FAQ about Layout
• Introduction to SKILL


• DRC (Design Rule Check) with Virtuoso


• LVS (Layout-Versus-Schematic) with Virtuoso


• Logic Simulation with Verilog

Netlist Extraction with Cadence:

• HSpice Netlist Extraction with Cadence


• Spectre Netlist Extraction with Cadence
• Spectre Simulation with Command Line
• Spectre Simulation with Analog Artisit (Graphical Interface)


• SOC Encounter: Place and Route Tool


• Import Verilog Netlist into Schematic


• Import GDS into Cadence Layout


• Pad Insertion


• Steps for Chip Submission

Navigation

Cadence Tutorial

Import Synthesized Design Into Cadence Virtuoso Layout View

 Author:  Jeannette Djigbenou

---

After running Place and Route on the synthesized design, you obtained a GDS file. You can use this GDS file to import the layout from SOC Encounter into Cadence Virtuoso Layout viewer. This will allow you to verify that the place-and-route tools have properly generated the design and that your design is DRC clean. You can verify this by:

• Importing the place-and-route layout to Cadence Virtuoso

• Importing the Verilog netlist into a schematic in Cadence Composer

• Running LVS on both views to verify that they have the same netlist.

This tutorial describes how you may import the layout from SOC Encounter into a Cadence Virtuoso Layout view. To run this tutorial, you need a GDS file, specifically TOP_COUNT.gds (from the vtvt_tsmc250_release/tutorial_files directory), exported from SOC Encounter. To learn how to get the GDS file, please refer to the appropriate instructions.

These steps describe how to import a GDS file into a Cadence Virtuoso Layout view.

• Make a new directory cad_test

• Setup directory cad_test to run Cadence icfb

• Add our standard cell library vtvt_tsmc250_nolabel into the cadence run directory cad_test.

• Copy the GDS file TOP_COUNT.gds into cad_test directory

• Start Cadence icfb

• In the CIW, go to File->Import->Stream…

• Fill in the StreamIn form as shown below. displays the form.

• Run Directory: .
  This is the current directory cad_test

• Input File: TOP_COUNT.gds
  The GDS file of the layout from SOC Encounter

• Top Cell Name: Leave this field blank.

• Library Name: vtvt_tsmc250_nolabel

Figure 1: StreamIn Form

• Select User-Defined Data: Fill it as shown below:

Layer Map Table: vtvt_tsmc250_StreamIn.map. This file converts the layers in the gds file into valid MOSIS layers. However, it contains extra layer numbers that are not compatible with MOSIS. For designs to be manufactured, use vtvt_tsmc250_nolabel.map in the Layer Map Table option.

Figure 2: User-Defined Data

• Select Options: Fill it as shown below

Figure 3: Options Form

• Click OK in the StreamIn form.

• A pop-up message will indicate that PIPO STRMIN completed successfully

• The cell TOP_COUNT in library vtvt_tsmc250_nolabel is created and contains the layout from SOC Encounter. Select cell TOP_COUNT layout view as shown on

Figure 4: Layout View of TOP_COUNT design

• The layout view of TOP_COUNT contains vtvt_tsmc250 standard cells. You may descend into each cell to view their layouts by selecting:

Design->Hierarchy->Descend…The layout of the standard cell selected will appear.

• Run DRC on the layout and correct any design errors.

  • In the layout view, go to Verify->DRC… and select OK.

• Your final design must be DRC clean.

You have completed this tutorial. You may want to verify that this layout, generated by the Place-and-Route tools, matches the synthesized netlist. This can be verified by running LVS between the schematic of the synthesized netlist and the extracted view of this layout.