Cadence Tutorial

Frequently Asked Questions about Layout

Authors:  Jeannette Djigbenou, Meenatchi Jagasivamani, Carrie Aust, Jia Fei



Q:  Do we use lambda rule or micron rule?

    • For the NCSU design kit, the units of the rules are in lambda.  Lambda is defined as 0.5*the minimum length.  The grid unit is lambda.
    • You can adjust the grid spacing by modifying the editor properties (Options->Display...).

Q:  What are the minimum transistor width and length?

    • For the NCSU design kit, the minimum length is 0.6 um and the minimum width is 0.9 um.

Q:  How do I recover cellviews if icfb crashes?

    Cadence keeps a temporary copy of the cellview that you are currently working on (called the panic cellview).  If cadence crashes, you can retrieve the panic cellview by typing dbOpenPanicCellView ("libname" "cellname" "viewname") in the CIW.  Here, libname is the library name, cellname is the name of your cellview, and viewname is either layout, schematic,...
    Open your cellview after restoring the panic cell.  DO NOT try to reopen the cellview before doing the dbOpenPanicCellView call or you've lost the panic cell.

Q:  Where can we find design rules for layout?

o    The technology file contains an outline of the DRC rules.  The rule file, divaDRC.rul is the file that is executed when the DRC operation is performed.

Q:  How can I create contacts and wires?

You can create contacts using the Create->Contact.  For wires, use Create->Path (the default size of the wire is the minimum width of the layer you have chosen in LSW, or the last size you set).

Q:  How do I give the contact for W = 0.4 um, when the contact width is 0.7 um?

The width of a transistor is the distance in the y-direction (in layout view) of the channel (where the poly overlaps the active region).  Thus, the y-distance of the contact area need not be the same as the y-distance (width) of the channel.

Q:  DRC Violation Question:  poly1 endcap < 0.50

You need to extend the poly to 0.5um past the active/diffusion area.

Q:  DRC Violation Question:  need pohmic within 5um of NMOS/ndiffR/nwellR/PNPvertical

You need a substrate/well contact within 5um of the FET, otherwise the contact resistance is too large.

Q: DRC Violation Question:  ndiff spacing to hot nwell < 2.60; substrate soft connected

There should be a VSS!/VDD! pin connected to the substrate/well contact.

Q:  DRC Violation Question:  off-grid errors

This error most often occurs when the grid resolution is too low.  The error means that the end coordinates of the layers are not on a grid.  Check to see if the grid-settings (Options->Display...) are correct.

Q: How to print.

Printing in Cadence
Open up your cellview.
goto the Design menu
Then click the 'plot options' button.
You probably want to click the center plot and fit to page buttons.

Down near the bottom, check the button near "send plot only to file" and type in a filename in the box next to it.. ie.

Uncheck the "mail log to" button

Then click OK and click OK on the submit plot page.

Now open up an xterm and change directory to the directory where your cadence files are. your file should be there.

type lp
(where is the file name of your schematic)

It should now print

Have fun!