Cadence Tutorial

Design Rule Check (DRC)

Author: Jeannette Djigbenou


There are process-specific design rules that describe how close layers can be placed together and what the sizes of the areas can be. These rules are given the minimum requirement to avoid a catastrophic failure of your circuit due to fabrication faults. You can use the following MOSIS SCMOS design rules as a guideline. The design rules are different for different processes.

The following is a procedure to perform design rule check (DRC) for a layout. DRC outputs any violations of the design rules for your technology process. This step is important because the violation of any design rules would cause the fabricated chip to not function as desired.

Before you start, you have to have a layout (view name: layout) in your library.


Have fun!