Cadence Tutorial
Post Layout - Transistor Level Simulation
with HSpice
Authors: Jinsik Yun, Dr. Dong S. Ha
Before you start this tutorial, you have to have the GDSII file exported from P&R procedure.
1. Required Files
- This is the sample GDS file: updown_counter.gds
- This GDS file was obtained from this verilog source (cnt_updown_syn.v) by using P&R
2. Layout import
- Using Layout Import tutorial, please import sample GDS file
- Open the imported layout. It should be like the below picture.
3. Labeling
- Please zoom in (You can use Window -> Zoom menu) two ports located in the left most side.
- Using 'Label' tool in the Tool bar, specify a appropriate label name and attach the label to the each ports. Please refer to the below picture.
- When labeling, please make sure that you selected 'text' pattern in the 'LSW' window.
- Please make sure that you labeled all ports
4. Extract HSpice netlist
- Exract the HSpice netlist using HSpice Netlist Extraction with Cadence
- If you succeeded the extraction, you can get the Netlist like this: updown_counter_from_cadence.sp
- You have to insert the stimulus and modify some .option statement as you can see the below pictures. This is the modified spice netlist: updown_counter.sp
This is the original netlist from Cadence.
This is the modified netlist.
5. Spice Simulation
- Using the modified netlist in the previous step, you can follow the spice simulation using HSpice simulation tutorial
- As a spice simulation result, you can get this waveform.
- You can also see the power analysis result from the log file.
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