Post Layout - Gate Level Simulation
with Synopsys VCS
Authors: Jinsik Yun, Dr. Dong S. Ha
Before you start this tutorial, you have to have the netlist and SDF(Standard Delay Format) file extracted from P&R
1. Setting testbench
- insert the $sdf_annotate Verilog system task within your initial statement of your testbench.
- This is the examples of testbench
2. Analyze and compile
- Once you complete $sdf_annotate setting, you can follow the same vcs test process as posted at 'VCS - Verilog Logic Simulation Tool'