--file name: tb_cnt_bhv.vhd
-- Test bench for cnt_bhv.vhd
Library IEEE;
use IEEE.std_logic_1164.all;
entity TB_CNT_BHV is
end;
architecture TESTBENCH of TB_CNT_BHV is
signal CLK,ENABLE,RESET : std_logic := '0';
signal COUNT: std_logic_vector(3 downto 0);
component CNT_BHV
port(CLK,ENABLE,RESET: in std_logic;
COUNT: inout std_logic_vector(3 downto 0));
end component;
begin
UUT :CNT_BHV
Port Map (
CLK,
ENABLE,
RESET,
COUNT
);
SignalSource : process
begin
ENABLE <= '0', '1' after 60 ns;
RESET <= '1', '0' after 40 ns;
CLK <= '1' , '0' after 50 ns, '1' after 100 ns, '0' after 150 ns,
'1' after 200 ns, '0' after 250 ns, '1' after 300 ns, '0' after 350 ns,
'1' after 400 ns, '0' after 450 ns, '1' after 500 ns, '0' after 550 ns,
'1' after 600 ns, '0' after 650 ns, '1' after 700 ns, '0' after 750 ns,
'1' after 800 ns, '0' after 850 ns, '1' after 900 ns, '0' after 950 ns,
'1' after 1000 ns, '0' after 1050 ns, '1' after 1100 ns, '0' after 1150 ns,
'1' after 1200 ns, '0' after 1250 ns, '1' after 1300 ns, '0' after 1350 ns,
'1' after 1400 ns, '0' after 1450 ns, '1' after 1500 ns, '0' after 1550 ns,
'1' after 1600 ns, '0' after 1650 ns, '1' after 1700 ns, '0' after 1750 ns,
'1' after 1800 ns, '0' after 1850 ns, '1' after 1900 ns, '0' after 1950 ns,
'1' after 2000 ns, '0' after 2050 ns, '1' after 2100 ns, '0' after 2150 ns;
wait;
end process;
end TESTBENCH;
configuration CFG_TB_CNT_BHV of TB_CNT_BHV is
for TESTBENCH
for UUT : CNT_BHV
end for;
end for;
end;