// This is the result of synthesis of top_count.vhd, stored in Verilog
// format (instead of VHDL), to be used with Cadence's Silicon Ensemble
// Ultra (seultra) Placement and Routing (PNR) tool.

module SMB_COUNT_0 ( CLK, CON, RESET, COUNT );
output [3:0] COUNT;
input  CLK, CON, RESET;
    wire n190, n191, n192, n193, n194, n195, n196, n197, n198, n199, n200;
    nor2_2 U54 ( .ip1(n191), .ip2(n192), .op(n190) );
    inv_2 U55 ( .ip(RESET), .op(n196) );
    nor2_2 U56 ( .ip1(n194), .ip2(n195), .op(n193) );
    inv_2 U57 ( .ip(COUNT[0]), .op(n191) );
    nand3_2 U58 ( .ip1(CON), .ip2(COUNT[1]), .ip3(COUNT[0]), .op(n194) );
    inv_2 U59 ( .ip(COUNT[2]), .op(n195) );
    xor2_2 U60 ( .ip1(COUNT[3]), .ip2(n193), .op(n197) );
    xor2_2 U61 ( .ip1(n194), .ip2(n195), .op(n198) );
    xor2_2 U62 ( .ip1(COUNT[1]), .ip2(n190), .op(n199) );
    xor2_2 U63 ( .ip1(CON), .ip2(COUNT[0]), .op(n200) );
    inv_4 U64 ( .ip(CON), .op(n192) );
    drp_1 \COUNT_reg<3>  ( .ck(CLK), .ip(n197), .rb(n196), .q(COUNT[3]) );
    drp_1 \COUNT_reg<2>  ( .ck(CLK), .ip(n198), .rb(n196), .q(COUNT[2]) );
    drp_1 \COUNT_reg<1>  ( .ck(CLK), .ip(n199), .rb(n196), .q(COUNT[1]) );
    drp_1 \COUNT_reg<0>  ( .ck(CLK), .ip(n200), .rb(n196), .q(COUNT[0]) );
endmodule


module SMB_COUNT_1 ( CLK, CON, RESET, COUNT );
output [3:0] COUNT;
input  CLK, CON, RESET;
    wire n190, n191, n192, n193, n194, n195, n196, n197, n198, n199, n200;
    nor2_2 U54 ( .ip1(n191), .ip2(n192), .op(n190) );
    inv_2 U55 ( .ip(RESET), .op(n196) );
    nor2_2 U56 ( .ip1(n194), .ip2(n195), .op(n193) );
    inv_2 U57 ( .ip(COUNT[0]), .op(n191) );
    nand3_2 U58 ( .ip1(CON), .ip2(COUNT[1]), .ip3(COUNT[0]), .op(n194) );
    inv_2 U59 ( .ip(COUNT[2]), .op(n195) );
    xor2_2 U60 ( .ip1(COUNT[3]), .ip2(n193), .op(n197) );
    xor2_2 U61 ( .ip1(n194), .ip2(n195), .op(n198) );
    xor2_2 U62 ( .ip1(COUNT[1]), .ip2(n190), .op(n199) );
    xor2_2 U63 ( .ip1(CON), .ip2(COUNT[0]), .op(n200) );
    inv_4 U64 ( .ip(CON), .op(n192) );
    drp_1 \COUNT_reg<3>  ( .ck(CLK), .ip(n197), .rb(n196), .q(COUNT[3]) );
    drp_1 \COUNT_reg<2>  ( .ck(CLK), .ip(n198), .rb(n196), .q(COUNT[2]) );
    drp_1 \COUNT_reg<1>  ( .ck(CLK), .ip(n199), .rb(n196), .q(COUNT[1]) );
    drp_1 \COUNT_reg<0>  ( .ck(CLK), .ip(n200), .rb(n196), .q(COUNT[0]) );
endmodule

module TOP_COUNT ( CLK, CON, RESET, COUNT1, COUNT2 );
output [3:0] COUNT2;
output [3:0] COUNT1;
input  CLK, CON, RESET;
// wire definitions
wire CLKi, CONi, RESETi;
wire [3:0] COUNT1i, COUNT2i;
// pad instantiations
// NOTE THAT THEY WERE ADDED MANUALLY - dc_shell DID NOT INSTANTIATE THEM
    padinc p0 (.pad(CLK), .di(CLKi));
    padinc p1 (.pad(CON), .di(CONi));
    padinc p2 (.pad(RESET), .di(RESETi));
    padout p30 (.do(COUNT1i[0]), .pad(COUNT1[0]));
    padout p31 (.do(COUNT1i[1]), .pad(COUNT1[1]));
    padout p32 (.do(COUNT1i[2]), .pad(COUNT1[2]));
    padout p33 (.do(COUNT1i[3]), .pad(COUNT1[3]));
    padout p40 (.do(COUNT2i[0]), .pad(COUNT2[0]));
    padout p41 (.do(COUNT2i[1]), .pad(COUNT2[1]));
    padout p42 (.do(COUNT2i[2]), .pad(COUNT2[2]));
    padout p43 (.do(COUNT2i[3]), .pad(COUNT2[3]));
    padvdd vdd_pad ();
    padgnd vss_pad ();
// original parts - the following lines WERE instantiated by dc_shell.
    SMB_COUNT_1 U0 ( .CLK(CLKi), .CON(CONi), .RESET(RESETi), .COUNT(COUNT1i) );
    SMB_COUNT_0 U1 ( .CLK(CLKi), .CON(CONi), .RESET(RESETi), .COUNT(COUNT2i) );
endmodule