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Request CAD Tools

Agreement and Disclaimer:

• A user who receives our tools agrees with the following terms:
• The tools should not be redistributed outside the his/her company or university.
• Any publication in which our tools have been used to obtain the results should cite the reference given below.
• The tools and accompanied information are provided "as is" without warranty of any kind.

To Receive Our Tools:

• Company
Companies can receive our tools through the industry affiliates program of CESCA. Companies are asked to join the Silver Membership of the affiliated program for a minimum of two years. The Silver membership fee is $5,000 per year. As an affiliated member of VISC, the company has other benefits such as access to VISC research findings and facilities. Please contact Dong Ha to join the affiliated program or for further information.
• University
The source code for our tools is released for teaching and research purposes only and should not be redistributed. This program, or any derivative thereof, may not be reproduced nor used for any commercial product without Dr. Dong Ha's written permission.

Contact person of a university should be a faculty member, not a student. When a new version or a new tool is available, we will inform the contact person by e-mail. If the contact person agrees with our distribution policy described above, he/she should fill in the form and submit it.

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Your Name:
	(Must be a faculty member)
Email:
	(Use Institution e-mail)
University:
	(No abbreviations)
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Country:
Department Website:
	(with a list of faculty members)
Comments:
	Security Confirmation: Please type the four letters displayed in the image.

Citation of References:

The following citations should be used for our tools.

 

ATALANTA		H.K. Lee and D.S. Ha, "Atalanta: an Efficient ATPG for Combinational Circuits,", Technical Report, 93-12, Dep't of Electrical Eng., Virginia Polytechnic Institute and State University, Blacksburg, Virginia, 1993.
FSIM		H.K. Lee and D.S. Ha, "An efficient forward fault simulation algorithm based on the parallel pattern single fault propagation," Proc. Int. Test Conf., pp. 946-955, October 1991.
SOPRANO		H.K. Lee and D.S. Ha, "SOPRANO: an efficient automatic test pattern generator for stuck-open faults in CMOS combinational circuits," Proc. Design Automatic Conf., pp. 660-666, June 1990.
HOPE		H. K. Lee and D. S. Ha, "HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, pp. 1048-1058, September 1996.