VTVT ASIC Design Flow

The VTVT ASIC design flow using standard cell libraries consists of using a VHDL or Verilog script to generate an entire design schematic and layout views for manufacturing. The design schematic and layout are combinations of the standard cells available on the VTVT site.

Each step of the flow links to a tutorial using VTVT Lab’s vtvt_tsmc250 standard cell library from TSMC 0.25 microns.

The design flow starts by implementing a VHDL script that describes the design functionality. The script is simulated then synthesized into a verilog netlist. The netlist is imported into Cadence ICFB as a schematic view and into Cadence SOC Encounter to generate a place-and-route layout view. Once the layout view is imported into Cadence ICFB, LVS is run to verify that the synthesized schematic and layout match. The design is then ready for chip submission.

Design Flow Map