Cell Libraries to Support VLSI Research and Education

Cell-based VLSI design - the most widely used approach in today's system-on-a-chip design - relies on a building-block infrastructure with standard cell libraries. All aspects of VLSI benefit from standard cell libraries, including full custom design, automatic layout generation, physical design, logic synthesis, CAD tools, and testing.

Commercial library cells are the supplier's proprietary information, and understandably, suppliers usually impose certain restrictions on the access and use of their library cells. Those restrictions on commercial library cells severely hamper VLSI research and teaching activities of academia. Our endeavor under the sponsorship of the National Science Foundation aims to address the problem. So researchers with academia can freely exchange their designs utilizing those library cells. In addition to our current TSMC 0.18 um, and TSMC 0.25 um cell libraries, we plan to develop and distribute cell libraries for TSMC 0.13 um; RAM compilers and data converters by the end of year 2008; and provision of additional features and simulation libraries.

Standard Cell Libraries

The VTVT Group has developed two standard-cell libraries targeting the TSMC 0.18um and TSMC 0.25um CMOS processes available via MOSIS. The libraries can be used with Synopsys synthesis tools and the Cadence SOC Encounter, Place/Route tool. All of the cells can be viewed and edited using the Cadence Virtuoso layout editor. The cell library requires NCSU design kit or other kits that follow MOSIS design rules. Since MOSIS DEEP design rules are used for our cell library, the NCSU design kit has been modified slightly. Changes to the NCSU kit are included in our distribution. Different minor updates are added to the release versions. Please refer to the download page for the current release version for each technology.

TSMC 0.18 um

This First Release of the VTVT Standard Cell library targeting the TSMC 0.18um, 1.8V CMOS process was on November 1, 2007.
We have included the following features:

TSMC 0.25um

In this Release 3 of the VTVT Standard Cell library targeting the TSMC 0.25um, 2.5V CMOS process, which has been released on December 21, 2006, we have added a symbol library. Symbols are now available for all our standard cells. They can be exported to Synopsys synthesis tool (Design Vision) and imported to Cadence schematic tool, Composer. The package for our cell library includes:

TSMC 0.35um

This First Release of the VTVT Standard Cell library targeting the TSMC 0.35um, 3.5V CMOS process was on July 24, 2009.
We have included the following features:

Useful Links:

Request for Our Standard Cell Library:
The cell library is available to universities and not-for-profit institutions at no charge. Companies can acquire the library for a nominal fee and should contact Prof. Dong S. Ha.

List of VTVT_TSMC180 Cells forTSMC 0.18 um 1.8 V CMOS Technology

List of VTVT_TSMC250 Cells forTSMC 0.25 um 2.5 V CMOS Technology

Comments: Please send us your comments, requests, and questions.

Acknowledgement:
We appreciate the financial support provided by the National Science Foundation under the program "Computer Research Infrastracure" of CCF (Computer & Communicatios Foundations) of CISE (Computer Information Science & Engineering). We are thankful to the support and the encouragement of Program Director Dr. Stephen Mahaney.


This material is based upon work supported, in part, by the National Science Foundation under Grant No. 0551652. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation.