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• Synopsys Unix Setup


• VHDL :
  • Scirocco and VirSim - A Logic Simulation Tool
  • Design Vision - A Logic Synthesis Tool
  • Power Estimation at the Gate Level
  
  
• Verilog
  • VCS-Verilog Logic Simulation
  • Design Vision - Verilog Logic Synthesis
  • Power Estimation at the Gate Level
• HSPICE
• NanoSim

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Synopsys Tutorial

Introduction

The objective of this home page is to give a tutorial to circuit designers who would like to get acquainted with Synopsys design tools. A step by step tutorial approach is adopted.  It is the hope of the author that by the end of this tutorial session, the user would have known how to do logic simulation and synthesis.

Those of you who have some basic knowledge of Synopsys tools already may prefer to jump ahead to your desired topic without fearing the loss of continuity.  Some topics might appear tedious, but be patient... there's light at the end of the tunnel.  Above all, have fun!  Isn't that what learning is supposed to be?

The Synopsys tools supported by these tutorials and their versions (when applicable) are:

• Synopsys: Y-2006.06-SP2

• VCS MX: Scirocco and VirSim: VirSim B-2008.12 Virtual Simulator Environment

• Design Compiler (in XG Mode): Version Y-2006.06-SP2 for linux -- Sep 01, 2006

• Design Vision: Version Y-2006.06-SP2 for linux -- Sep 01, 2006

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Front End Design

• Synopsys Unix Setup


• VHDL :
  • Scirocco and VirSim - A Logic Simulation Tool
  • Design Vision - A Logic Synthesis Tool
  • Power Estimation at the Gate Level
  
  
• Verilog :
  • VCS-Verilog Logic Simulation
  • Design Vision - Verilog Logic Synthesis
  • Power Estimation at the Gate Level
  
  
• SystemC :
  • SystemC Installation

Back End Design

• HSPICE : Analog SPICE Simulation
• NanoSim : Fast Ananlog SPICE Simulation