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• Layout with Virtuoso


• Inverter Tutorial with Virtuoso
• Capacitor and Resistor Layout
• FAQ about Layout
• Introduction to SKILL


• DRC (Design Rule Check) with Virtuoso


• LVS (Layout-Versus-Schematic) with Virtuoso


• Logic Simulation with Verilog

Netlist Extraction with Cadence:

• HSpice Netlist Extraction with Cadence


• Spectre Netlist Extraction with Cadence
• Spectre Simulation with Command Line
• Spectre Simulation with Analog Artisit (Graphical Interface)


• SOC Encounter: Place and Route Tool


• Import Verilog Netlist into Schematic


• Import GDS into Cadence Layout


• Pad Insertion


• Steps for Chip Submission

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Cadence Tutorial

Layout with Virtuoso

Authors: Jeannette Djigbenou, Meenatchi Jagasivaman, and Jia Fei

After developing a schematic of your design, the next step in the design flow is creating a layout of your design using Cadence Virtuoso. A layout describes the masks from which your design will be fabricated. The layers in a layout describe the physical characteristics of the device and have more details than a schematic. Therefore, layout verification of your design is critical.

There are two types of layout design: Full-Custom and Automated. Full-custom layout is when the user physically draws all of the layers for the individual transistor. This is a very tedious process, but usually enables results in a compacter design than the automated process. The automated process, on the other hand, is done by instantiating standard cells (reusing basic blocks) and usually takes more area, but it is much faster.

To get you acquainted with the layout process, a tutorial has been developed that describes the procedure to custom layout an inverter. Please go through it.

This following is the usual steps followed for the layout:

1. Layout Transistors and Routing...
2. Creating I/O Pins
3. Design Rule Check (DRC)

Layout Transistors and Routing...

The first step in layout design is to layout the transistors in your circuit. Where the transistors are placed can be critical in getting the most compact design. Also, it is important to make sure that all important nodes are accessible for routing. After the transistors have been implemented, the next step is to make the necessary routing connections. Usually, for large circuits, routing can take up as much as 50% of the total area. Hence, it is a good idea to think about the floorplanning of your design before you start the layout.
You can look at the Inverter Tutorial to get a basic introduction to what the necessary components are.

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Creating I/O Pins

Once you have finished creating the layout, the next step is to add the I/O pins of your circuit. It is necessary to add the vdd! and vss! connections to your circuit for the purpose of DRC. The following is a procedure to add I/O pins to your circuit:

Before you start, you have to have a layout (view name: layout) in your library.

• From your Layout window:
  1. Choose Create->Pin... from the menu.The Create Pin form will appear.
  2. If the form is titled "Create Shape Pin", choose "sym pin" under the Mode option.
  3. Enter a TerminalName(the name of your pin).
     • NOTE: For HSPICE, there is a node name limit of 16 characters.
  4. Make sure that the "Display Pin Name" option is selected.
  5. Specify the "I/O Type" as either input, output, or inputoutput.
  6. Specify the Pin Type as either Metal1_T, Metal2_T,... depending on which is the top layer at the place that the pin is to be inserted.
  7. Specify the Pin Width to the desired pin width (the pin is square).
  8. Move the mouse to specify where the pin and the label should be placed.
  9. Repeat the above process (1-7) for all the pins in your circuit.

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Design Rule Check (DRC)

Go to the DRC Section of the Cadence Tutorial, to get the DRC procedures.