Education
- Virginia Tech, Ph.D. Candidate, Electrical Engineering, (August 2003 - present)
- Virginia Tech, M.S., Electrical Engineering, (August 2001 - August 2003)
- Tsinghua University, Beijing, China, B.S., Electrical Engineering, (August 1997 - July 2001)
Research Interests
- Frequency Synthesizers
- High-speed Data Converters
- Low-noise RF ICs
Experience
- RFIC Design Engineer at Qualcomm Inc., Campbell, CA, (October 2006 ~ present): Working on the PLL design including phase frequency detector, charge pump, ultra high-speed divider, prescaler and TCXO.
- Intern at Intel Corporation, Chandler, AZ, (January 2006 ~ August 2006): Worked with senior design engineers in advanced component division (ACD) group, and mainly involved in the design of a decision feedback equalizer and a DLL using 65 nm technology.
- GRA, VLSI for Telecommunications Group, Virginia Tech, (August 2003 ~ December 2005): Designed a high-speed CMOS D/A converter and implemented a PLL-based frequency synthesizer using TSMC 0.18um CMOS technology for front-end transceivers, including phase-frequency detector, charge pump, LC tank VCO, frequency divider.
- GRA, Center of Power Electronics System (CPES), Virginia Tech, (August 2001 ~ August 2003): Worked on high-frequency magnetic component design for power management
Publications
- Shen Wang, Dong S. Ha, Sang S. Choi, "Design of a 6-bit 5.4-Gsamples/s CMOS D/A Converter for DS-CDMA UWB Transceivers", IEEE International Conference on Ultra-Wideband, pp.333-338, September 2005
- Shen Wang, M. A. de Rooij, W. G. Odendaal, J. D. Van Wyk, D. Boroyevich, "Reduction of High Frequency Conduction Losses using a Planar Litz Structure", IEEE Transactions on Power Electronics, vol. 20, pp.261-267, March 2005.
Relevant Courses
- Analog VLSI Design
- RF IC Design
- Design of Systems On a Chip
- Digital VLSI Design
- Digital Communications
- Phase-Locked Loop
- Radio Engineering
- Nonlinear Communication Circuits
- Digital Signal Processing
