Education
- Virginia Tech, Blacksburg, PhD Candidate - ECE, (Aug. 2003 - present)
- Sogang University, Seoul, Korea , M.S., Electrical Engineering, (Feb. 1995 - Feb. 1997)
- Sogang University, Seoul, Korea , B.S., Electrical Engineering, (Feb. 1991 - Feb. 1995)
Research Interests
- Reconfigurable architecture
- Parallel computing
- High speed VLSI circuit design
Experience
- Principal design engineer, AMD Inc., Boxborough MA (Mar. 2006 - Present) Worked on Implementation of next generation x86 64-bit CPU. Worked on High-speed digital circuit design for FBDIMM interface. Worked on DDR2/3 Interface implementation. Performed logic/circuit implementation, P&R, SAPR, timing analysis, verification, and spice simulation
- Senior engineer, Qualcomm Inc., San Diego, CA (Jan. 2005 - Feb. 2006) Performed verification/emulation of GPS Searcher/ GSM/ EDGE modem. Developed verification framework.
- GRA, Virginia Tech VLSI for Telecommunications Lab, Virginia Tech, Blacksburg, VA (Aug. 2003 - Jan. 2005) Performed architecture design using SystemC. Performed analysis of CDMA system and MPEG4/ H.264 AVC video system. Implemented target algorithms in simulation model. Performed circuit implementation. Performed architecture design using SystemC. Implemented the code generator of WCDMA/CDMA2000. Implemented the VTRM simulation model.
- Staff engineer, Telechips Inc., Seoul, Korea (Jul. 2000 - Jul. 2003) Defined specification and architecture. Designed logic blocks (Digital Audio Interface, General Serial I/O, CD Interface block, DPLL block for CD spindle motor, USB1.1 Interface and USB Host Interface) Performed functional verification, timing verification, DFT design, fault simulation, ATPG. Developed FPGA validation board. Developed system firmware (Digital Audio Player system, SSFDC file system, USB OHCI) Developed MP3 Real-time encoding Algorithm of which complexity is half of conventional algorithm
- Senior engineer, Samsung Electronics Company, Kihung, Yong-In, Korea (Feb. 1997 - Jul. 2000) Performed failure analysis and circuit modeling of critical path. Worked on 1GHz Alpha processor development with COMPAQ. Performed high speed CMOS circuit modeling, coupling analysis (MOSCRITIC), static timing analysis (Zrace, Zeist). Developed CAD tools that contributed to minimize the verification period. Characterized library cells to obtain parameters used in verification tools.
- GRA, CAD and Computer systems Lab, Sogang University, Seoul, Korea (Feb. 1995 - Feb.1997) Developed power conscious high-level synthesis algorithms. Worked on developing a GUI environment of SODAS-LP system
Publications
- A Novel high-level synthesis algorithm for Low power ASIC Design, Journal of Microelectronic System Integration, 1996
- Power-conscious scheduling algorithm for performance-driven datapath synthesis, ELECTRONICS LETTERS, Aug 1996
- Efficient synthesis algorithm for low-power ASIC design, ELECTRONICS LETTERS, Oct. 1996.
- Reconfigurable Modem Architecture for CDMA based 3G Handsets, SDR Forum's technical conference 2005
- FleXilicon: a reconfigurable architecture for multimedia and wireless communications, IEEE ISCAS, May 2006
- High speed adder design for low precision addition, IEEE ISCAS, 2007
Relevant Courses
- Digital Signal Processing Architectures
- Parallel Computer Architectures and Algorithms
- Analysis & Design of Analog Integrated Circuits
- Simulation and Testing of Digital Systems
- Electric Acoustics
- Floating Point Integrated Circuit
- Advanced Computer Architecture
- Microprocessor System Design
- Silicon Compiler and Design Automation
- Advanced VLSI Design I,II
- Software Radio
- CMOS memory circuit design
- System On Chip Design
